1. Field of the Invention
The present invention relates to a voltage-current converting method and a voltage-current converting circuit. In particular, the present invention relates to an active matrix type display apparatus using a current drive type display device and a current programming type pixel circuit, and a voltage-current converting method of the display apparatus.
2. Description of the Related Art
In recent years, self-luminous type displays using light emitting devices have been watched as next generation displays. Among them, the application and the development of an organic electroluminescence (EL) device, which is a current control type light emitting device, the light emission luminance of which is controlled by the current flowing through the element, have been actively performed. An organic EL display including the peripheral circuitry thereof uses thin film transistors (TFTs) not only in the display area thereof but also in the peripheral circuitry. A conventional image display panel (hereinafter referred to as an EL panel) that applies EL elements, which are such self-luminous elements, as image display elements and uses the TFTs in the display area thereof and the peripheral circuitry thereof will be described with reference to the attached drawings.
FIG. 12 illustrates an example of the configuration of an EL panel including conventional current setting system pixel circuits.
In an EL panel 100 illustrated in FIG. 12, a pixel display unit 9 and the peripheral circuitry thereof are arranged. In the pixel display unit 9, EL elements, the number of which is equal to the number of R, G, B primary colors, and pixel circuits 2 composed of TFTs for controlling the currents input into the EL elements are two-dimensionally arranged in a matrix of N columns by M rows. A horizontal scanning control signal 11a is input from the outside into an input circuit 6 in the peripheral circuitry. Moreover, a vertical scanning control signal 12a is input from the outside into an input circuit 7. Furthermore, an auxiliary column control signal 13a is input from the outside into an input circuit 8.
A horizontal scanning control signal 11 (including a horizontal clock signal and a horizontal scanning start signal) converted by the input circuit 6 is input into a column shift register 3. Moreover, a vertical scanning control signal 12 converted by the input circuit 7 is input into a row shift register 5. A row scanning signal 20 output from each output terminal of the row shift register 5 is input into the pixel circuits 2 on each row through a scanning line.
Moreover, an auxiliary column control signal 13 converted by the input circuit 8 is input into each of gate circuits 4 and 16. A first horizontal sampling signal 17 output from each terminal of the column shift register 3 is input into a horizontal sampling signal gate circuit 15 together with a control signal 21 converted by the gate circuit 16. A second horizontal sampling signal 18 converted by the horizontal sampling signal gate circuit 15 is input into column current generation circuits (also referred to as “column current control circuits” or “column control circuits”) 1 together with a video signal (voltage signal) 10 input from the outside and a control signal 19 converted by the gate circuit 4. A column control signal 14, which is a current signal converted from a video signal by the column current generation circuit 1, is input into the pixel circuit 2 of each column through a data line.
The plurality of column current generation circuits 1 are arranged according to the number of primary colors of each column of the pixel circuits 2, and are configured to cope with each number of primary colors of the input video signal 10. Each of the column current generation circuits 1 is configured by using a voltage-current converting circuit converting a dot sequential voltage video signal into a line sequential current video signal by the line.
FIG. 13 illustrates an example of the configuration of a voltage-current converting circuit constituting the column current generation circuit 1 described in U.S. Pat. No. 7,126,565. Incidentally, a gate, a source, and a drain of a transistor will be denoted by brevity codes of /G, /S, and /D, respectively, and a signal and a signal line for supplying the signal will be similarly represented without distinguishing them as the occasion demands in the following description. Transistors M5 and M12 among transistors M1-M12, which are TFTs, are p-channel TFTs (PMOSs) and the other transistors are n-channel TFTs (NMOSs). The transistors M3 and M9 are column current generating drive transistors (NMOS current drive transistors).
A video signal video, sampling signals SPa and SPb, and control signals P1-P6, each of which constitutes the control signal 19, are input into the column current generation circuit 1 illustrated in FIG. 13. The video signal video is connected to the M1/S and the M7/S, and the sampling signals SPa and sampling signal SPb are connected to the M1/G and M7/G, respectively. The M1/D is connected to a capacitor C1, and the other end of the capacitor C1 is connected to a capacitor C2, one end of which is grounded, and the transistor M3/G, the source of which is grounded. The M3/D and the M3/G are connected to the M2/D and the M2/S, respectively, and the control signal P1 is connected to the M2/G. The M3/D is connected the M4/S; the M4/D is connected to the short-circuited gate and drain of the transistor M5, the source of which is connected to a power source voltage VCC; and the M4/G is connected to the control signal P2. Furthermore, the M3/D is connected to the M6/S; the M6/D is connected to a terminal from which a current signal i (data) is output; and the M6/G is connected to the control signal P3. On the other hand, the M7/D is connected to a capacitor C3, and the other end of the capacitor C3 is connected to a capacitor C4, one end of which is grounded, and the gate of the transistor M9, the source of which is grounded. The M9/D and the M9/G are connected to the M8/D and the M8/S, respectively, and the control signal P4 is connected to the M8/G. The M9/D is connected to the M11/S; the M11/D is connected to the short-circuited gate and drain of the transistor M12, the source of which is connected to the power source voltage VCC; and the M11/G is connected to the control signal P5. Furthermore, the M9/D is connected to the M10/S; the M10/D is connected to the terminal outputting the current signal i (data); and the M10/G is connected to the control signal P6.
FIG. 14 is a time chart for describing the operation of the column current generation circuit 1 illustrated in FIG. 13. FIG. 14 illustrates the operation for three horizontal scanning periods of a video signal, or for three lines of the EL panel.
First, just before a time t1, each of the sampling signals SPa and SPb is the L level, and the control signals P1-P6 are L, L, H, L, H, and L levels, respectively. Each of the transistors M1, M2, M4, M6, M7, M8, M11, and M10, which perform switching operations, are in the following state: M1=OFF, M2=OFF, M4=OFF, M6=ON, M7=OFF, M8=OFF, M11=ON, and M10=OFF, respectively. At this time, the transistors M3 and M9 are current-driven by holding voltages Va1 and Vb1 charged in the capacitor attended to each of their gate electrodes, respectively. That is, the current Ia1 of the M3/D is output as the current signal i (data), and becomes the column control signal 14. The current of the M9/D is supplied to the transistor M12, and the voltage of the M9/D is determined.
Next, at the time t1, the input video signal video is at the blanking level Vb1. At this time point, the sampling signal SPa, and the control signals P2, P3, P5, and P6 change to the H, H, L, L, and H levels, respectively. Consequently, each of the transistors M1, M2, M4, M6, M7, M8, M11, and M10, which perform switching operations, are in the following state: M1=ON, M2=OFF, M4=ON, M6=OFF, M7=OFF, M8=OFF, M11=OFF, and M10=ON, respectively. At this time, as the current signal i (data), the current Ib1 of the M9/D driven by the voltage Vb1 of the M9/G is output in the place of the current Ia1 of the M3/D. Before a time t2, the control signal P1 changes to the H level, and the transistor M2 turns to ON. The M3/G is charged by the transistor M5 in a short period of time from this time point to a time t2.
Next, at the time t2, the charging operation of the M3/G by the transistor M5 stops, and the M3/G performs a self-discharge operation it gradually approaches its own threshold voltage Vth. Next, at a time t3, the sampling signal SPa changes to the L level, and the transistor M1 turns to OFF. Before a time t4, the control signal P1 changes to the L level, and the transistor M2 turns OFF. Then, the self-discharge operation of the transistor M3 ends at this time point. During the period from this time point to the time t4, both the transistors M2 and M4 turn OFF, and the M3/D quickly changes to be at the L level. Consequently, the voltage of the M3/G somewhat drops owing to the drain-to-gate capacitor of the transistor M3 and the like as illustrated in FIG. 14.
Next, at the time t4 when the control signal P2 changes to the H level, the transistor M4 turns ON, and the M3/D again rises. Consequently, the voltage of the M3/G again rises to return to the almost original state as illustrated in FIG. 14. At this time point, because the voltage of the M3/G is a voltage Vrsa in the neighborhood of its own threshold voltage Vth, the current of the M3/D is almost zero. In an effective period of the video signal video from the time t1 to a time t7, the sampling signal SPa, which is a horizontal sampling signal group, is generated, but the sampling signal SPb is not generated.
Next, in a period of from a time t5 to a time t6, by the horizontal sampling signal SPa of a column corresponding to the period, the voltage of the M3/G changes from the voltage Vrsa in the neighborhood of its own threshold value Vth by a voltage AV1 according to a video signal level d1 based on the blanking level Vb1. The voltage AV1 can be roughly expressed by AV1=d1×C1/(C1+C2+C(M3)). The C(M3) denotes gate input capacitor of the transistor M3. At this time, the drive current Id of the transistor M3 is expressed by: Id=β×ΔV2 (where β denotes a drive coefficient, and ΔV=Vgs−Vth). After that, when the corresponding sampling signal SPa changes to the L level, the transistor M1 turns OFF, and the voltage of the M3/G changes to the voltage Va2, which somewhat drops owing to the parasitic capacitor operation of the transistor M1, and the voltage again becomes the held state.
After shifting to the next horizontal scanning period, at the time t7, the input video signal video has become the blanking level Vb1, and the sampling signal SPb and the control signals P2, P3, P5, and P6 change to the H, L, H, H, and L levels, respectively. A drive current Ia2 of the transistor M3 driven by the voltage Va2 of the M3/G is output as the current signal i (data) in place of the current Ib1 of the M9/D.
In a period of from that time to a time t13, a voltage Vb2 of the M9/G, which voltage Vb2 is increased from a voltage (Vrsb) in the neighborhood of the own threshold voltage Vth by a voltage ΔV2 corresponding to a video signal level d2 based on the blanking level Vb1, is sampled and held by the operation similar to the one mentioned above. And then at the time t13, the current signal i (data) is changed from the drive current Ia2 of the transistor M3 mentioned above to a drive current Ib2 of the transistor M9, which drive current Ib2 is driven by the voltage Vb2 of the M9/G.
When the operation has shifted to the further next horizontal scanning period, after the time t13 on, a voltage Va3 of the M9/G, which voltage Va3 is increased from a voltage (Vrsa) in the neighborhood of the own threshold voltage Vth by a voltage ΔV3 corresponding to a video signal level d3 based on the blanking level, is sampled and held by the operation similar to the one mentioned above.
However, because the aforesaid column current generation circuit used in the conventional display apparatus uses NMOS transistors as current drive transistors for the generation of column currents, characteristic variations of their voltage-current converting characteristics among elements are larger in comparison with those of PMOS transistors. In particular, the variations of the drive currents Id caused by the drive coefficient β among the voltage-current converting characteristics expressed by the formula Id=β×(Vgs−Vth)2 are not settled by the conventional circuits, such as the column current generation circuit 1 disclosed in the U.S. Pat. No. 7,126,564 mentioned above. Consequently, current values supplied to EL elements vary every column of pixel circuits, and then the light emission luminance of the EL elements varies every column. In the worst case, the variations appear as vertical line noises on a display area, and the vertical line noises are one of the primary factors of image quality deteriorations. Consequently, the settlement of the variations of the current values has been desired.